1. Field of the Invention
The present invention relates generally to microelectronic circuits, and more particularly, to trenched gate MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) having laterally merged body layers formed by a process with reduced masking sequences.
2. Description of the Related Art
Power semiconductor devices have long been used as replacement for mechanical relays in various applications. Development in semiconductor technology enables these power devices to operate with high reliability and performance. However, modern day instruments are now built at a miniaturized scale with lower power consumption. These instruments, such as fast switching power supplies, high-frequency ballasts, robotics controls and various portable machines, all require power devices to operate under certain stringent requirements. Accordingly, special criteria have to be met in the design and manufacturing of these devices. One area that shows prominence is the fabrication of power metal oxide semiconductor field effect transistors (MOSFETs) using trenched gates.
In a trenched gate MOSFET array, intersecting trenches which define a plurality of cells are formed on a silicon substrate. The trenches are filled with conductive material separated from the silicon substrate with a thin layer of insulating material. There are also other diffusion layers, such as the body and source layers, of different impurity types and concentration deposited in the semiconductor substrate. As arranged, the conductive and insulating materials in the trenches constitute the gate and gate oxide layer, respectively, of the MOSFET. In addition, the perimeter and the depth of the cell correspond to the respective channel width and depth of each MOSFET cell.
Power MOSFETs with trenched gates provide many advantages. To begin with, the channels of the MOSFETs are arranged in a vertical manner, instead of horizontally as in most planar configurations. The consequential benefit is that a higher degree of integration on a semiconductor substrate can be realized. More importantly, since the channel direction is vertical, the lateral current paths are basically eliminated. As a result, the overall channel resistance is reduced. Reduction in channel resistance substantially curtails ohmic loss during the power-on state of the MOSFET, which in turn provides lower power consumption and further alleviates heat dissipation.
Heretofore, fabricating a trenched gate MOSFET has involved a substantial number of fabrication steps in the manufacturing process. To highlight the number of masks and the associated steps involved, FIGS. 1A-1R schematically illustrate the conventional process required to fabricate a trenched MOSFET.
The fabrication process starts with providing a n-type base silicon wafer 4 as shown in FIG. 1A. An epitaxial layer 6 with a predetermined resistivity is then grown atop the base wafer 4 as shown in FIG. 1B. A field oxide layer 8 is thereafter deposited on the top of the epitaxial layer 6. The resultant structure 2 up to this step is shown in FIG. 1C.
A first mask M1, called the active mask, which defines the active area 10 and the termination area 12 is disposed atop the filled oxide layer 8 as shown in FIG. 1D. The active mask M1 is a photoresist layer capable of being patterned by the conventional photolithographic process. After proper patterning, using the patterned first mask M1 as a shield, either the method of dry etch or wet etch is employed to define the field oxide layer 8 as shown in FIG. 1E. The field oxide layer 8 defines an active body layer 14 (formed by the next step) which has to be at a distance d away from the scribe line 36 of the structure 2. The scribe line 36 is a physical cut line separating the semiconductor dies in a finished wafer. The reason of this critical requirement will be explained later in this specification.
The method of ion implantation is then employed to form the active body layer 14 and the termination body layer 16. After a proper drive-in process, the active body layer 14 and the terminal body layer 16 are diffused sufficiently deep into the epitaxial layer 6. The resultant structure up to this step is shown in FIG. 1E.
Another layer of oxide 18 is then deposited on the top of the structure 2 as shown in FIG. 1F. A second mask M2, called the trench mask, is then spun on the top of the oxide layer 18. The second mask M2 is also made of photoresist material. After proper patterning and etching, the resultant structure 2 up to this step is shown in FIG. 1G. Using the trench mask M2 as a shielding mask, the oxide layer 18 is then etched to define a pattern with trench openings 20 in the oxide layer 18 as shown in FIG. 1H. The trench mask M2 is then removed. Using the patterned oxide 18 as a masking layer and via the method of either dry or wet etch, the structure 2 is then anisotropically etched to form trenches 22 in the epitaxial layer 6 as shown in FIG. 1I.
What follows is the formation of a gate oxide layer. First, the oxide layer 18 is removed. The trenches 22 are then lined with gate oxide 24 and are thereafter filled with polycrystaline silicon 26 as shown in FIG. 1J. The process of planazation is then employed to flatten the polycrystalline silicon 26 as shown in FIG. 1K. The polycrystalline silicon 26 is thereafter doped with phosphorous oxychloride (POCl.sub.3) to assume a n-type conductivity. The resultant structure 2 up to this step is shown in FIG. 1K.
The next step is the formation of a source layer in the structure 2. First, the polycrystalline silicon 26 is further etched. A third photoresist mask M3, called the source blocking mask, is then laid on the top of the structure 2. After proper patterning, the resultant structure 2 up to this step is as shown in FIG. 1L. Arsenic (As) is then implanted through the M3 mask into the body layer. After a drive-in process, the source layer 28 is formed in the body layer 14 as shown in FIG. 1M. Thereafter, the third mask M3 is removed and a passivation oxide layer 30 is formed on the top of the structure 2 as shown in FIG. 1M.
A fourth photoresist mask M4, called the contact mask, is then laid atop the passivation oxide layer 30. After proper patterning, the resultant structure up to this step is shown in FIG. 1N. The process of contact etch is then performed. After the removal of the contact mask M4, the resultant structure 2 is covered with a patterned passivation oxide layer 30 as shown in FIG. 10.
P-type material, such as boron, is then implanted and diffused into the structure 2 through the patterned passivation oxide layer 30, resulting in contact diffusion layers 29 formed in the structure 2 as also shown in FIG. 10.
The step of metallization follows. A metal layer 32 is deposited atop the structure 2 by the sputtering process as shown in FIG. 1P. A fifth photoresist mask M5, called the metal mask, is then deposited and patterned on the top of the metal layer 32 as shown in FIG. 1Q. The metal layer 32 is then etched through the fifth mask M5. Furthermore, a drain metal layer 34 is deposited on the bottom side of the wafer 4. The resultant structure 2 up to this step is as shown in FIG. 1R.
Not shown in FIG. 1A-1R is the deposition of another masking step via a 6th mask M6, called the bonding pad mask, for the purpose of exposing selected areas of the metal layer 32 to the bonding wires, after a protective insulating layer is deposited atop the structure 2.
In the process of fabricating a trenched MOSFET device as depicted above, there are at least 6 photoresist masks, namely, M1-M6 involved. As with other thin-film microelectronic processes, it is always highly desirable to reduce the number of masks with the associated masking and patterning steps. The advantage of reducing the number of masks in the fabrication process is twofold. First, laying a mask on a semiconductor structure in the manufacturing process is relatively expensive, not merely in the cost of the mask itself but the various patterning and etching steps associated with the mask involved. Secondly, the more the number of masking and etching steps involved, the higher the chance of contamination of the structure and consequently the lower production yield of the final products. Accordingly, the costs saved by reducing a mask is beyond the prorated basis accorded by the reduced mask.
In the production of a trenched MOSFET device, there has been a long-felt need in the industry to curtail the number of masks and the associated fabrication steps involved, without sacrificing any device performance.